As a conventional semiconductor memory device which has a plurality of electrically erasable and programmable read only memory cells, each being capable of storing two bits of information, there is known a cell transistor as shown schematically in FIG. 23. In a channel forming region in a substrate 11, between diffusion regions 12A and 12B in the substrate 11, there are provided an insulating film 13 and a control gate electrode 15, on both sides of which there are provided insulating films 14 and word line electrodes 16.
As for the memory cell of this sort, reference is made for example to    (1) A Novel 2-Bit/Cell MONOS Memory Device with a Wrapped-Control-Gate Structure That Applies Source-Side Hot Electron Injection, 2002 Symposium on VLSI Technology Digest of a Technical Papers, p206 to 207;    (2) Japanese Patent Kokai Publication JP-P2001-230332A (JP Patent Application 2000-269892);    (3) Japanese Patent Kokai Publication JP-P2002-26149A (JP Patent Application 2000-180763);    (4) Japanese Patent Kokai Publication JP-P2001-357681A (JP Patent Application 2000-180760);    (5) U.S. Pat. No. 6,399,441; and    (6) U.S. Pat. No. 6,388,293.
As another configuration of the memory cell, storing two bits of information per cell, such a structure shown in FIG. 24 has been proposed. In the undermentioned publication (10) (Japanese Patent Kohyo Publication JP-P2001-512290A), for example, it is stated that a non-volatile memory of the MONOS (metal-ONO-silicon) structure, including, as a gate insulating film 14, which comprises a silicon oxide film formed on a substrate, a silicone nitride film formed on the silicon oxide film and a silicon oxide film formed on the silicone nitride film, referred to as an oxide nitride oxide (ONO) film, is able to store 2-bit data per cell in a charge trapping film (silicon nitride film) sandwiched between silicon oxide films directly below the gate electrode. In an EEPROM (Electrically Erasable and Programmable Read Only Memory), having a charge trapping film and 2-bit storage node per cell, two separate bits, that is a left side node Node1, and a right side node Node2, are formed in spatially spaced apart regions in the charge trapping film. The two bits (storage nodes) are read in the opposite direction to the direction in which the bits were programmed. For example, the Node2 is programmed in the charge trapping film in the ONO film 14 by applying a positive write voltage across the gate electrode 16 and the drain diffusion region 12B, as the source diffusion region 12A is grounded, for injecting sufficiently accelerated hot electrons into a region adjacent to the drain diffusion region 12B of the charge trapping film in the ONO film 14. The stored bits are read in the opposite direction to the direction in which the bits were written, that is by applying the positive electrode to the source electrode 16 and the source diffusion region 12B, as the drain diffusion region 12B is grounded. The memory cell is erased by applying a suitable erase voltage to for example the gate electrode 16. For erasing the Node2, the erase voltage is applied to the drain diffusion region 12B and, for erasing the Node1, the erase voltage is applied to the drain diffusion region 12A for expelling the electrons from the charge trapping film. Thus, by applying preset gate, drain and the source voltages, two bits can be independently stored in the left and right regions of the charge trapping film directly below the gate electrode.
This sort of the memory cell has been disclosed in for example the    (7) U.S. Pat. No. 6,011,725;    (8) U.S. Pat. No. 6,256,231;    (9) Japanese Patent Kokai Publication JP-P2001-156189A (JP Patent Application 2000-306999); and    (10) Japanese Patent Kohyo Publication JP-P2001-512290A (JP Patent Application 2000-505640).
The 2-bit cell MONOS memory device, described in the above Publication (1), is now explained in detail.
In the above Publication (1), there are shown a cross-sectional view and an equivalent circuit of the MONOS memory of the one-cell two-bit configuration, shown in FIGS. 25A to 25C, as well as the bias conditions for the write, erase and read operations.
The memory cell includes paired impurity diffusion regions (paired bit lines), provided in the substrate surface, plural control gates CG provided on the silicon oxide film between the neighboring diffusion regions in the substrate surface, and plural word lines WL extending in a direction perpendicular to the control gates on the ONO film on both sides of the silicon oxide film in the substrate surface, to carry out programming and erasure for the nodes by source side hot electron injection and by hot hole electron injection, respectively.
In the Publication (1), the respective storage sites below the word line WL[j] on the right hand side of the control gate CG [1+2n] are programmed in parallel. The bit line BL [I+2n−1] is set to the ground potential, the bit line BL [I+2n] is biased to 5.0V, while the word line WL[j] is biased to 9.0V. The control gate CG[I+2n] is biased to 1.0V/0.0V to induce/suppress the source side hot electron injection. The information stored on the right hand side of the control gate is erased by hot hole injection produced by the bias conditions of FIG. 25C. During read, the bit line BL[I+2n−1] is biased to 1.5V, while the bit line BL [i+2n] is biased to 0.0V, the word line WL[j] is biased to Vread and the control gate CG [I+2n] is biased to 1.5V. For programming/erasing the storage site for the left hand side of the control gate CG [I+2n], the bias conditions for the bit line BL [I+2n−1], BL [I+2n] are exchanged. The respective bits of the memory cells are read by applying the reverse read, as indicated in FIG. 25C.